Hardware Implementation of Subsampled Adaptive Subband Digital Predistortion Algorithm.

Power amplifiers play a crucial role in communication systems since they have a direct impact on the power consumption of mobile phones and base stations. Digital predistortion (DPD) is a correction technique for power amplifiers that has a growing interest because of its completely digital implementation and because of its gains in linearity.

This technique requires a feedback path in which an analog-to-digital converter (ADC) is a critical element. Up to now, the distorted signals could be digitized using high-performance analog-to-digital converters (ADC). But, the expected increase in bandwidth for new telecommunication standards will require even wider bandwidths for the DPD feedback path and larger computational resources. The power consumption caused by the additional parts for the DPD may limit the overall efficiency gain of the linearized system particularly for small-cells base stations. Recently, subband approaches have been proposed to relax the design constraints 1of the feedback path ADC and the digital processing unit in order to minimize the energy consumption of the DPD.

In this presentation we will present a hardware implementation of a subband digital predistortion system. The subband approach enables the use of subsampling that is exploited to reduce the sampling rate. Simulation results show that the convergence of the algorithm is not affected by this subsampling. The hardware implementation is then discussed along with synthesis results that shows the impact of the clock frequency on the expected power consumption of the circuit.